The basic transfer cycle on the Micro Channel is a minimum of 200 ns (100 ns for the address and 100 ns for the data which results in five million basic transfer cycles per second for a device running in burst mode. As shown in Figure "Basic Data Transfer Mode", a data transfer operation is done in two steps. First the address for the transfer (either I/O adapter or memory location) is selected, then up to four bytes of data is moved across the data buffer.
Depending of the width of the data path (8, 16, or 32 bits) the instantaneous data transfer rate on the channel would be 5, 10, or 20MB per second.
The matched-memory extension is a modification to the basic data transfer mode, which can improve the data transfer capabilities between the system master and channel-attached memory. When supported, it allows the basic transfer cycle of 200 ns to be reduced.
The DMA controller on the system board requires two basic transfer cycles to move either 8 bits or 16 bits of data. It moves the data from the originator to a buffer in the DMA controller and then to the target device or memory location. Because two cycles are used per 8 or 16 bits of data, the data transfer rate for DMA controllers is 2.5MB or 5MB per second.