Because the range of LDT selectors is only 512 Meg, addresses less than this can be transformed to use an LDT selector, with restrictions. The transformation is to append three low-order 1 bits to the value, and to discard three high order zero bits. An alternative way of stating this is to multiply by 8, then add 7. The three low order one bits are LDT (table indicator=1), and PL=3. The restrictions are that the storage must be PL=3 application storage, must not span a 64K boundary in the linear address space, and the value must be less than hex 2000 0000.
0 0 0 2 1 4 B 0 <--- Linear Address 0000 0000 0000 0010 0001 0100 1011 0000 <--- Binary shift the left half 3 bits to the left, which gives 0000 0000 0001 0000 0001 0100 1011 0000 <--- Binary add 7 to the left half ( 0111 binary ) 0000 0000 0001 0111 0001 0100 1011 0000 <--- Binary 0 0 1 7 : 1 4 B 0 <--- Hex Sel:Offset Note that the lower 16 bits, or offset, are unchanged.