FPU Flags Affected

The floating-point instruction pages have a section called "FPU Flags Affected," which tells how each instruction can affect the four condition code bits of the FPU status word. These pages contain a condition code information table similar to the following:

┌──┬──┬──┬──┐
│C0│C1│C2│C3│
├──┼──┼──┼──┤
│? │* │? │? │
└──┴──┴──┴──┘

The first row of the table lists the names of the floating-point condition code flags. The entries in the second row are filled in according to how the flag is affected by the instruction:

┌────────┬────────────────────────────────┐
│VALUE   │MEANING                         │
├────────┼────────────────────────────────┤
│<blank> │Instruction does not affect flag│
├────────┼────────────────────────────────┤
│0       │Instruction clears the flag     │
├────────┼────────────────────────────────┤
│1       │Instruction sets the flag       │
├────────┼────────────────────────────────┤
│?       │Instruction's effect on the flag│
│        │is undefined                    │
├────────┼────────────────────────────────┤
│*       │Instruction modifies the flag   │
│        │(either sets or clears depending│
│        │on operands)                    │
└────────┴────────────────────────────────┘

The four FPU condition code bits (C0, C1, C2, and C3) are similar to the flags in a CPU; the processor updates these bits to reflect the outcome of arithmetic operations. The effect of these instructions on the condition code bits is summarized in the following table:

Condition Code Interpretation ┌─────────────────────────┬─────────────┬────────────┬────────────┬────────────┐
│ INSTRUCTION │ C0 │ C3 │ C2 │ C1 │
├─────────────────────────┼─────────────┴────────────┼────────────┼────────────┤
│ FCOM, FCOMP, FCOMPP, │ Result of Comparison │ Operands │ Zero or │
│ FTST, FUCOMPP, FICOM, │ │ is not │ O/U# │
│ FICOMP │ │ Comparable │ │
├─────────────────────────┼──────────────────────────┴────────────┼────────────┤
│ FXAM │ Operand class │ Sign or │
│ │ │ O/U# │
├─────────────────────────┼─────────────┬────────────┬────────────┼────────────┤
│ FPREM, FPREM1 │ Q2 │ Q1 │ 0=reduction│ Q0 or O/U# │
│ │ │ │ complete │ │
│ │ │ │ │ │
│ │ │ │ 1=reduction│ │
│ │ │ │ incomplete │ │
├─────────────────────────┼─────────────┴────────────┴────────────┼────────────┤
│ FIST, FBSTP, FRINDINT, │ UNDEFINED │ Roundup or │
│ FST, FSTP, FADD, FMUL, │ │ O/U# │
│ FDIV, FDIVR, FSUB, │ │ │
│ FSUBR, FSCALE, FSQRT, │ │ │
│ FPATAN, F2XM1, FYL2X, │ │ │
│ FYL2XP1 │ │ │
├─────────────────────────┼──────────────────────────┬────────────┼────────────┤
│ FPTAN, FSIN, FCOS, │ UNDEFINED │ 0=reduction│ Roundup or │
│ FSINCOS │ │ complete │ O/U# │
│ │ │ │ (UNDEFINED │
│ │ │ 1=reduction│ if C2=1) │
│ │ │ incomplete │ │
├─────────────────────────┼──────────────────────────┴────────────┼────────────┤
│ FCHS, FABS, FXCH, │ UNDEFINED │ Zero or │
│ FINCSTP, FDECSTP, Con- │ │ O/U# │
│ stant Loads, FXTRACT, │ │ │
│ FLD, FILD, FBLD, FSTP │ │ │
│ (ext. real) │ │ │
├─────────────────────────┼───────────────────────────────────────┴────────────┤
│ FLDENV, FRSTOR │ Each bit loaded from memory │
├─────────────────────────┼────────────────────────────────────────────────────┤
│ FLDCW, FSTENV, FSTCW, │ UNDEFINED │
│ FSTSW, FCLEX │ │
├─────────────────────────┼─────────────┬────────────┬────────────┬────────────┤
│ FINIT, FSAVE │ Zero │ Zero │ Zero │ Zero │
└─────────────────────────┴─────────────┴────────────┴────────────┴────────────┘

NOTES:

O/U#

When both IE and SF bits of status word are set, this bit distinguishes between stack overflow (C1=1) and underflow (C1=0).
Reduction
If FPREM and FPREM1 produces a remainder that is less than the modulus, reduction is complete. When reduction is incomplete the value at the top of the stack is a parial remainder, which can be used as input to further reduction. For FPTAN, FSIN, FCOS and FSINCOS, the reduction bit is set if the operand at the top of the stack is too large. In this case, the original operand remains at the top of the stack.
Roundup
When the PE bit of the status word is set, this bit indicates whether the last rounding in the instruction was upward.
UNDEFINED
Do not rely on any specific value in these bits.

The condition code bits are used primarily for conditional branching. The FSTSW AX instruction stores the FPU status word directly into the AX register, allowing these condition codes to be inspected efficiently. The SAHF instruction can copy C3 - C0 directly to the CPU's flag bits to simplify conditional branching. The following table shows the mapping of these bits to the CPU flag bits.

┌────────────┬────────────┐│FPU FLAG    │IU FLAG     │
├────────────┼────────────┤
│C0          │CF          │
├────────────┼────────────┤
│C1          │(None)      │
├────────────┼────────────┤
│C2          │PF          │
├────────────┼────────────┤
│C3          │ZF          │
└────────────┴────────────┘

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