Operation

The "Operation" section contains an algorithmic description of the instruction which uses a notation similar to the Algol or Pascal language. The algorithms are composed of the following elements:

• Comments are enclosed within the symbol pairs "(*" and "*)".

• Compound statements are enclosed between the keywords of the "if" statement (IF, THEN, ELSE, FI) or of the "do" statement (DO, OD), or of the "case" statement (CASE ... OF, ESAC).

• Execution continues until the END statement is encountered.

• A register name implies the contents of the register. A register name enclosed in brackets implies the contents of the location whose address is contained in that register. For example, ES:[DI] indicates the contents of the location whose ES segment relative address is in register DI. [SI] indicates the contents of the address contained in register SI relative to SI's default segment (DS) or overridden segment.

• Brackets are also used for memory operands, where they mean that the contents of the memory location is a segment-relative offset. For example, [SRC] indicates that the contents of the source operand is a segment-relative offset.

• A  B; indicates that the value of B is assigned to A.

• The symbols =, <>, ≥, and ≤ are relational operators used to compare two values, meaning equal, not equal, greater or equal, less or equal, respectively. A relational expression such as A = B is TRUE if the value of A is equal to B; otherwise it is FALSE.

• A * B indicates that the value of A is multiplied by the value of B.

The following identifiers are used in the algorithmic descriptions:

• OperandSize represents the operand-size attribute of the instruction, which is either 16 or 32 bits. AddressSize represents the address-size attribute, which is either 16 or 32 bits. For example,

  IF instruction = CMPSW THEN OperandSize  16;
  ELSE
  IF instruction = CMPSD
  THEN OperandSize  32;
  FI;
  FI;
  

  indicates that the operand-size attribute depends on the form of the CMPS instruction used. Refer to the explanation of address-size and operand-size attributes at the beginning of this chapter for general guidelines on how these attributes are determined.

• StackAddrSize represents the stack address-size attribute associated with the instruction, which has a value of 16 or 32 bits, as explained earlier in the chapter.

• SRC represents the source operand. When there are two operands, SRC is the one on the right.

• DEST represents the destination operand. When there are two operands, DEST is the one on the left.

• LeftSRC, RightSRC distinguishes between two operands when both are source operands.

• eSP represents either the SP register or the ESP register depending on the setting of the B-bit for the current stack segment.

The following functions are used in the algorithmic descriptions:

• Truncate to 16 bits(value) reduces the size of the value to fit in 16 bits by discarding the uppermost bits as needed.

• Addr(operand) returns the effective address of the operand (the result of the effective address calculation prior to adding the segment base).

• ZeroExtend(value) returns a value zero-extended to the operand-size attribute of the instruction. For example, if OperandSize = 32, ZeroExtend of a byte value of -10 converts the byte from F6H to doubleword with hexadecimal value 000000F6H. If the value passed to ZeroExtend and the operand-size attribute are the same size, ZeroExtend returns the value unaltered.

• SignExtend(value) returns a value sign-extended to the operand-size attribute of the instruction. For example, if OperandSize = 32, SignExtend of a byte containing the value -10 converts the byte from F6H to a doubleword with hexadecimal value FFFFFFF6H. If the value passed to SignExtend and the operand-size attribute are the same size, SignExtend returns the value unaltered.

• Push(value) pushes a value onto the stack. The number of bytes pushed is determined by the operand-size attribute of the instruction. The action of Push is as follows: IF StackAddrSize = 16 THEN
  IF OperandSize = 16
  THEN
  SP  SP -2;
  SS:[SP]  value; (* 2 bytes assigned starting at byte address in SP *)
  ELSE (* OperandSize = 32 *)
  SP  SP -4;
  SS:[SP]  value; (* 4 bytes assigned starting at byte address in SP *)
  FI;
  ELSE (* StackAddrSize = 32 *)
  IF OperandSize = 16
  THEN
  ESP  ESP -2;
  SS:[ESP]  value; (* 2 bytes assigned starting at byte address in ESP*)
  ELSE (* OperandSize = 32 *)
  ESP  ESP -4;
  SS:[ESP]  value; (* 4 bytes assigned starting at byte address in ESP*)
  FI;
  FI;
  

• Pop(value) removes the value from the top of the stack and returns it. The statement EAX  Pop( ); assigns to EAX the 32-bit value that Pop took from the top of the stack. Pop will return either a word or a doubleword depending on the operand-size attribute. The action of Pop is as follows: IF StackAddrSize = 16
  THEN
  IF OperandSize = 16
  THEN
  ret val  SS:[SP]; (* 2-byte value *)
  SP  SP + 2;
  ELSE (* OperandSize = 32 *)
  ret val  SS:[SP]; (* 4-byte value *)
  SP  SP + 4;
  FI;
  ELSE (* StackAddrSize = 32 *)
  IF OperandSize = 16
  THEN
  ret val  SS:[ESP]; (* 2 byte value *)
  ESP  ESP + 2;
  ELSE (* OperandSize = 32 *)
  ret val  SS:[ESP]; (* 4 byte value *)
  ESP  ESP + 4;
  FI;
  FI;
  RETURN(ret val); (*returns a word or doubleword*)
  

  Pop ST is used on floating-point instruction pages to mean pop the FPU register stack.

• Bit[BitBase, BitOffset] returns the value of a bit within a bit string, which is a sequence of bits in memory or a register. Bits are numbered from low-order to high-order within registers and within memory bytes. In memory, the two bytes of a word are stored with the low-order byte at the lower address.

  If the base operand is a register, the offset can be in the range 0..31. This offset addresses a bit within the indicated register. An example, 'BIT[EAX, 21]' is illustrated in the following figure.
  Bit Offset for BIT[EAX,21]
  

  ┌──────────────────────────────────────────────────────┐
  │     31            21                            0    │
  │   ┌──────────────┬──┬────────────────────────────┐   │
  │   └──────────────┴──┴────────────────────────────┘   │
  │                                                    │
  │                    │                             │   │
  │                    └────────BITOFFSET=21─────────┘   │
  │                                                      │
  └──────────────────────────────────────────────────────┘
  

  If BitBase is a memory address, BitOffset can range from -2 gigabits to 2 gigabits. The addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)), where DIV is signed division with rounding towards negative infinity, and MOD returns a positive number. This is illustrated in the following figure.
  Memory Bit Indexing
  

  ┌──────────────────────────────────────────────────────┐
  │   7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0    │
  │   ┌──┬──┬────────┬────────────────┬──────────────┐   │
  │   └──┴──┴────────┴────────────────┴──────────────┘   │
  │   │  BITBASE+1   │    BITBASE     │   BITBASE-1  │   │
  │                                  │                  │
  │       └──────OFFSET=+13───────────┘                  │
  │                                                      │
  │                                                      │
  │   7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0    │
  │   ┌──────────────┬────────────────┬──────────────┐   │
  │   └──────────────┴────────────────┴──────────────┘   │
  │   │  BITBASE     │   BITBASE-1    │   BITBASE-2  │   │
  │                  │                                  │
  │                  └─────OFFSET=-11───────┘            │
  │                                                      │
  └──────────────────────────────────────────────────────┘
  

• I-O-Permission(I-O-Address, width) returns TRUE or FALSE depending on the I/O permission bitmap and other factors. This function is defined as follows: IF TSS type is 16-bit THEN RETURN FALSE; FI;
  Ptr [TSS+66]; (* fetch bitmap pointer *)
  BitStringAddr  SHR (I-O-Address, 3) + Ptr;
  MaskShift  I-O-Address AND 7;
  CASE width OF:
  BYTE: nBitMask  1;
  WORD: nBitMask  3;
  DWORD: nBitMask  15;
  ESAC;
  mask  SHL (nBitMask, MaskShift);
  CheckString  [BitStringAddr] AND mask;
  IF CheckString = 0
  THEN RETURN (TRUE);
  ELSE RETURN (FALSE);
  FI;
  

• Switch-Tasks is described in detail in the Intel documentation.