Clocks Columns

Each "Clocks" column gives the approximate number of clock cycles the instruction takes to execute on that particular processor. The clock count calculations makes the following assumptions:

• Data and instruction accesses hit in the cache.

• The target of a jump instruction is in the cache.

• No invalidate cycles contend with the instruction for use of the cache.

• Page translation hits in the TLB.

• Memory operands are aligned.

• Effective address calculations use a base register which is not the destination register of the preceding instruction.

• No exceptions are detected during execution.

• There are no write-buffer delays.

The following symbols are used in the clock count specifications:

• n, which represents a number of repetitions.

• m, which represents the number of components in the next instruction executed, where the entire displacement (if any) counts as one component, the entire immediate data (if any) counts as one component, and every other byte of the instruction and prefix(es) each counts as one component.

• pm:, a clock count that applies when the instruction executes in Protected Mode. pm: is not given when the clock counts are the same for Protected and Real Address Modes.

When an exception occurs during the execution of an instruction and the exception handler is in another task, the instruction execution time is increased by the number of clocks to effect a task switch. This parameter depends on several factors:

• The type of TSS used to represent the new task (32 bit TSS or 16 bit TSS).

• Whether the current task is in V86 mode.

• Whether the new task is in V86 mode.

• Whether accesses hit in the cache.

• Whether a task gate on an interrupt/trap gate is used.

The following table summarizes the task switch times for exceptions, assuming cache hits and the use of task gates.

Task Switch Times for Exceptions ┌───────────────────────────────┬──────────────────────────────────────────────┐│ OLDTASK │ NEWTASK │
│ ├───────────────┬───────────────┬──────────────┤
│ │ TO 32 BIT TSS │ TO 16 BIT TSS │ TO VM TSS │
├───────────────────────────────┼───────────────┼───────────────┼──────────────┤
│ VM/32 bit/16 bit TSS │ 85 │ 87 │ 71 │
└───────────────────────────────┴───────────────┴───────────────┴──────────────┘