When data is stored in memory or on any external device, the integrity of the data is typically ensured by having some sort of checking information stored with the data. Using this information, lost or incorrect bits may be detected and in certain cases corrected (on advanced memory systems and I/O adapters). The buses that comprise the Micro Channel are normally regarded as extremely safe conduits of information and are therefore not usually checked. While the chance of an error on the buses is very small, a missing or extra bit could still be induced by:
To improve the integrity of the buses, the Micro Channel architecture supports address parity and data parity as an option for devices that are able to handle this function.
Odd parity is used and is implemented by using formerly reserved lines as new address and data parity lines. To indicate that parity is used/checked two new control lines are defined: APAREN (Address Parity Enabled) and DPAREN (Data Parity Enabled).
If a master addresses a slave with APAREN enabled, the slave will answer only if the parity is correct. If not, the bus master suspends the operation and sets an internal error flag.
During write operations from a bus master to a slave device, the slave is responsible for the parity checking if the DPAREN line is active. The slave should then indicate bad parity by activating the CHCK (Channel Check) signal. If a bus master detects a parity error during a read operation with the DPAREN line activated (by the slave), it is expected to suspend the operation and set an internal error flag.
Address parity and data parity are both optional and can be used independently of each other. Devices that use the parity checking and devices that do not are permitted to coexist in the same Micro Channel system.