In "conventional" personal computer architectures such as the original IBM PC and PC AT, the system bus formed the data path, by which hardware components exchanged information with one another. The bus operated under the direct control of the system's main processor, and could handle only a single task at any time.
The Micro Channel architecture defines a set of specifications for a high-speed data "highway" connecting the system processor or processors, memory, I/O devices, and hardware adapters. The main feature that distinguishes the Micro Channel from the older PC bus is that the system processor does not have exclusive control of it but other processors and intelligent adapter cards, which are connected to the channel, can take charge of it and initiate data transfers across it. The mechanism, by which control of the Micro Channel is shared amongst the competing subsystems, is known as arbitration. The Micro Channel consists of a number of buses, controlled by the bus arbitration unit, which operate independently of the system's main processor. The main components of the Micro Channel are:
The arbitration bus and its associated signals are used by the bus arbitration unit to prioritize and resolve up to 16 concurrent requests by intelligent devices (known as masters) for control of the channel. The system processor has the lowest priority level, leaving 15 levels available for other processors and intelligent devices in the system. Although the system processor is defined to have the lowest priority level, it always "owns" the channel whenever the channel is not being used by another device. The arbitration unit resolves contending requests, and selects one device as the temporary owner of the channel; this device is then known as the controlling master. The controlling master may then perform a single data transfer or if the channel had been requested in "burst mode", multiple data transfers. For "burst transfers", the controlling master owns the channel until the transfer is complete or another arbitration participant requests ownership of the channel. In such cases the controlling master must relinquish ownership of the channel within 7.8 microseconds.
The arbitration controller has a fairness algorithm built into it to ensure that subsystems with high priority do not monopolize the channel at the expense of lower priority subsystems. There is also a feature known as pre-emption, which allows a subsystem with an urgent requirement to request and be given control of the channel even though another subsystem is currently using it.
The address bus and its associated signals are used by the controlling master to select a slave to be the source or target for a data transfer. The Micro Channel addressing consists of two separate address spaces:
The data bus is used to transfer 8, 16, 24, or 32 bits of data between two masters or between a master and a slave. The associated control signals indicate the width and direction (read or write) of the transfer.
The Micro Channel architecture defines the physical properties of the circuits and all the timings and signal sequences of signals on these circuits.
The Micro Channel architecture is extensible in that it has been possible to include new features in the architecture while maintaining compatibility with existing devices. All Micro Channel devices are expected to support certain basic functions. Mechanisms are provided which allow a device that supports an optional feature to communicate its capability to a partner device, with which it is exchanging data. If both devices support the feature then it is enabled for the data transfer operation, if appropriate. If one device supports a feature and the other device does not, they may still communicate with one another. Obviously that feature cannot be used during the data transfer operation.