The 80386 supports the Intel 80287 and 80387 numeric coprocessors. Support is also provided within the instruction set for multiple 80386 processors within the same system, sharing memory and other resources. This support is provided through the LOCK prefix instruction. When specified in conjunction with another instruction, the LOCK prefix instruction ensures that the locking processor has exclusive use of the requested resource.
Only a few 80386 instructions can be used with the LOCK prefix instruction. It is typically used to prefix instructions like BTC (Bit Test and Complement) where it locks the area of memory defined by the destination operand for as many cycles as necessary to update the entire operand.
In several instances, the processor itself automatically locks activities on the data bus. For example, when acknowledging interrupts, switching tasks, loading descriptors from the LDT to the segment selector, and updating the page table ACCESS and DIRTY bits, the required memory pages are locked since these are highly critical operations.
The 80386 includes on-chip memory caching to improve performance. The processor must therefore allow for the case where data in shared memory is modified and where that data is currently recorded in a cache on another processor. In such situations, the 80386 employs an interprocessor interrupt to let other processors know when such a change has been made.
This is normally done by using one of the physical address pins on the chip, and having the receiving processor implement a task switch when it receives this signal. The task switch clears the system registers, reloads the new descriptors and invalidates the memory cache in the processor.
Note that by changing the function of one of the addressing pins, however, the physical addressing capability of the processor is reduced to 2GB.