Physical Characteristics

These individual units are connected by 32-bit buses and operate in parallel to provide a six-stage pipelined execution of instructions. This implies that up to six different instructions may be held concurrently within the chip, at different stages of execution. To further improve performance, the 80386 uses on-chip caching and implements sophisticated memory management and bit manipulation (such as a 64-bit barrel shifter) in hardware.

The 80386 chip contains eight 32-bit general registers. To provide compatibility with the 8086 and 80286 processors, the 80386 provides the capability to use the lower-order 16 bits of these registers to represent the 16-bit registers used in these preceding processors. This is illustrated in Figure "80386 General, Segment, and Status Registers".

Programs running in virtual 8086 mode may utilize the full register set of the 80386 (all 32-bit registers including the new FS, GS, debug, control, and test registers). The programs can also use instructions with 32-bit operands by overriding the operand size by including an operand size prefix on the instruction.

The 80386 also provides six 16-bit segment registers, which are used to contain segment selectors, thus providing support for the same segmented memory model used in the 80286 processor. Note that the FS and GS segment registers are new in the 80386.

The instruction pointer (EIP) register and the flags (EFLAGS) register are both 32-bit registers.

Applications written for the 80286 run unmodified on the 80386. This is because the 80286 instructions, addresses, limits, segment types, etc., are a subset of those available in 80386, and run in 16-bit mode automatically. The 80386 handles this very simply; if the upper word (16 bits) of a memory reference is zero, then that reference must be an 80286 reference.

The registers described above are available to application programmers, either directly using assembly language or indirectly through the use of higher-level programming languages. The 80386 processor provides a number of additional registers which are available for use by the operating system. These registers are protected and are not accessible by application programs:

• GDTR (global descriptor table register)
  
• LDTR (local descriptor table register)
  
• IDTR (interrupt descriptor table register)
  
• TR (task register).

Four control registers (CR0 to CR3) are used to hold pointers to data structures used by the paged memory model and for status information. These registers are new in the 80386 processor, since previous processors did not support the paged memory model.

Eight debug registers (DR0 to DR7) are provided to aid in real-time system and application debugging. These registers are also new in the 80386.

Two test registers (TR6 and TR7) are provided to allow for verification of the integrity of the translation lookaside buffer hardware used by the processor's paging subsystem.